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Reference number: 6993

Developed by Prof Wayne Luk in the Department of Computing, Imperial College London .


A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. Orders-of-magnitude improvements in performance and power efficiency have been achieved in software designs, for applications such as financial modelling and signal processing. Effective Utilities for Run-timE Configuration Adaptation (EURECA) is a novel FPGA architecture for supporting effective dynamic data access (DDA) in reconfigurable devices, based on run-time configuration adaptation; essentially on-the-fly reconfiguration.

The unbalanced technological advancements in processor and memory in modern computer systems have led to the “memory wall” problem. Compared with arithmetic operations, a data-access operation takes a CPU main about 400-times longer. Therefore, cache ‘misses’ introduce large penalties in performance and power consumption. Bounded by the memory wall, applications with random data access achieve significantly lower performance and scalability compared with applications with linear data access. This makes data management the primary concern of computing systems today, especially for critical applications with random data access, such as graph problems, sparse matrix processing, web services, and database operations.

FPGAs provide a platform to accommodate customised architectures to accelerate specific applications. Efficient and scalable memory architecture can be constructed for linear data access. However, in order to support parallel random data access, an all-to-all crossbar is required for a customised architecture with N memory ports and N parallel data-paths. As an example, a simple multiply-and-accumulate kernel with 32-to-32-bit parallel memory ports and a 32-to-32 crossbar (common in large scale FPGA devices) cannot be placed and routed. Given that current customised architectures often contain hundreds of data-paths and a 64-bit data width, the expensive crossbar prohibits efficient support of random data accesses in existing FPGA architectures.



  • High performance for applications with DDA
  • Considerable area reduction
  • Flexible memory management (Memcached applications)
  • Parallel sorting (Sorting applications)
  • Random data access reorganisation (Sparse and Graph applications)
  • Compared with conventional static designs, EURECA provides up to:
    • 15x reduction in area
    • 2.2x increase in clock frequency (reduction in critical path delay)
    • 33x reduction in area-delay

Dynamic Data Access applications including:

  • Memcached
  • Sorting
  • Sparse Matrix
  • Graph


EURECA is a novel reconfigurable architecture that efficiently supports random data access on-chip and off-chip. Instead of implementing all possible connections between data-paths and memory ports, the EURECA architecture only configures the active connection at each clock cycle, and reconfigures the implemented configurations cycle-by-cycle. An on-chip configuration generator updates configurations based on runtime variables. Experimental results show that key applications with random data access (such as social networks, fluid flow simulation, and database management) can be efficiently supported, with radical area reduction and clock frequency increase.

Intellectual Property

UK Priority Application Number: 1414286.3

Download the datasheet


Rebeca Santamaria-Fernandez

Director of Industry Partnerships and Commercialisation, Engineering


+44 (0)20 7594 8599

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